In many electronic systems, data can be transmitted or received without an accompanying timing reference. For example, a read-head of a hard disk drive can transmit a stream of data that flows from sender to receiver with no accompanying clock even though the receiver may be required to process the data synchronously. Therefore, clock or timing information related to the data must be recovered from the data at the receiver. Clock and data recovery is the process of recovering clock or timing information. A decision feedback equalizer (DFE) is a critical block in clock data recovery. It can equalize a received signal without degrading signal to noise ratio.
DFEs use information retrieved from previously received pulses of data to eliminate inter-symbol interference (ISI) on a current pulse of data. More specifically, the distortion on a current pulse that was caused by previous pulses is subtracted from the current pulse. If the values of symbols that have previously been detected are known, then the ISI contributed by these symbols can be canceled out exactly by subtracting past symbol values using appropriate weighting. As a part of this process, the trailing inter-symbol interference, caused by previous symbols, is reconstructed and subtracted.
FIG. 1 shows a diagram of a conventional half-rate DFE. The half-rate DFE of FIG. 1, is implemented using current mode logic (CML). It includes two summers, six CML latches, two CML multiplexors, two CML-to-complementary metal oxide semiconductor (CMOS) converters, synchronization CMOS circuits for the next stage, CML buffers (not shown) and dual clocks (a CML and a CMOS clock). The DFE provides an output that is received by a CMOS serialization-deserialization (SerDes) circuit (not shown in FIG. 1). Shortcomings of conventional DFE circuits such as that shown in FIG. 1 include a non-trivial level of complexity in both circuit and clock distribution aspects of their design. In addition, such circuits consume an excessive amount of power due to the amount of silicon involved in their implementation and because they process signals in voltage mode.